Background information respecting the 80386, its characteristics and its use in microcomputer systems including cache memory subsystems are described in Intel's "Introduction to the 80386", April 1986 and the 80386 Hardware Reference Manual (1986). The characteristics and operating performance of the 82385 are described in the Intel publication "82385 High Performance 32-Bit Cache Controller" (1987).
In microcomputer systems, as in other computer systems, speed of operations is an important criterion which in most cases has to be balanced against system cost. Many features which were first introduced to speed up operations in mainframe computers and minicomputers are now finding their way into microcomputer systems. These include cache memory subsystems and pipelined operations.
In some microcomputer systems (for example those employing the Intel 80386), pipelined operations are an attractive operating option. For 80386/82385 microcomputer systems the 82385 cache controller provides an NA signal which it is suggested should be connected to a corresponding input on the 80386. This allows the 82385 to assert the NA signal to the 80386 prior to completion of a given bus cycle to enable the 80386 to output information (data, address and/or control) for the next operating cycle. The timing is arranged, along with connected components, so that if a cache operation is the given operation, information for the given operation has already been accepted by the cache memory and therefore changing the 80386 output information to correspond to the next cycle will not interfere with the operation which is in the process of being completed. This also holds true for situations in which a cache miss condition has occurred requiring reference not to the cache memory but to main memory since access to main memory is via latched buffers which therefore store information respecting the given operation.
The 80386 also has the capability of operating with what is referred to as dynamic bus sizing. The 80386 is nominally a 32-bit machine, i.e. the width of the data bus is 32 bits. However, the 80386 can operate with 16-bit devices (devices which will transfer only 16 bits of data) by responding to a BS16 signal which is provided to the 80386 to indicate the presence of a 16-bit device. The BS16 signal is important to the 80386 in the event that it has performed a 32-bit operation. Of course the 16-bit device cannot, in one operation, transfer the 32 bits of data which the 80386 is capable of generating and/or accepting. Thus, a second operation (cycle) is necessary and the 80386 responds to the BS16 signal to automatically generate the next, necessary, cycle.
In order for this type of operation to be successful when the 82385 is present it is also necessary for the 82385 to have information respecting the character of the device taking part in the operation so that the NA signal to the 80386 is not improvidently generated. As described in the referenced Intel publications the 82385 requires device information at the beginning of a cycle in contrast to the 80386 which can accept and act on device information substantially later in the cycle.
In some microcomputer systems, this constraint is accepted by correlating the address of a device with its size so that for example all 32-bit devices are in a first predetermined address range and all 16-bit devices are in a second, different address range. By this technique then, the size of a device can be determined by its address.
However, in systems which require the flexibility of locating a wide variety of devices within widely varying address ranges, this constraint cannot be complied with. One class of such systems are those employing the IBM Micro-Channel (TM) bus.
In many systems, including systems of the foregoing type, a device when addressed will return an indication of its size. However, since the 82385 requires device size information to be available at the beginning of a bus cycle, in systems where this information is only available later in the cycle, there is the possibility of an improvident NA signal.
Therefore it is an object of the present invention to provide an arrangement in an 80386/82385 microcomputer system which selectively controls the NA signal so that it is coupled to the 80386 only under appropriate circumstances. In other circumstances the NA signal is prevented from reaching the 80386. Preventing the NA signal from reaching the 80386 prevents pipelined operation, i.e. it prevents the generation of information for a next cycle before the given cycle has been completed. With this flexible control of the NA signal, the microcomputer system can now operate with dynamic bus sizing, i.e. it can now operate with devices of various sizes without information at the beginning of the cycle as to the size of the device being operated with.
Cacheable devices, i.e. devices generating data which can be cached, are necessarily 32-bit devices. All such devices have addresses (specifically, tags) indicating cacheability. All other devices (whether or not 32-bit devices) have addresses indicating information they generate will not be found in cache. Control of the NA signal depends in part on cacheability. Specifically, since any cacheable device is a 32-bit device, there is no question of improvident NA signals when operating with cacheable devices. Furthermore, in the event of a cache hit, there is no question but that the NA signal is appropriate since only cacheable devices (32-bit devices) will produce a cache hit. Thus an important feature of allowing dynamic bus sizing and pipelined operations is preventing or inhibiting the NA signal from reaching the 80386 in the event of assertion of an address to a non-cacheable device.
If, during the course of a given cycle (where the NA signal has been inhibited), it turns out the device is a 32-bit device, then the cycle completes in normal fashion (without pipelining). On the other hand, if it turns out during the course of the cycle that the device being operated with is a 16-bit device (and the cycle is a 32-bit cycle), then the 80386 generates the additional, necessary cycle. This operation is entirely transparent to the 82385, i.e. the 82385 takes no part in controlling the second of the two cycles. Finally, if the device being operated with turns out to be an 8-bit device, then the 80386 "sees" a 16-bit device so that it operates exactly as has been described for the case when the device is a 16-bit device. In other words, the 80386 "sees" a 16-bit device so that after the first cycle is completed (during which cycle it is informed that it is operating with a 16-bit device), a second cycle is generated. However, not only transparent to the 82385, but also transparent to the 80386, other logic converts each of the 16-bit cycles of the 80386 into two 8-bit cycles. Thus in the case where a 32-bit cycle is directed at an 8-bit device, the 82385 takes no part in the operation, the 80386 generates two 16-bit cycles, and other logic operates on each of the 80386 16-bit cycles to generate two 8-bit cycles.
Thus in accordance with one aspect, the invention provides a microcomputer system with pipelined instruction sequencing responsive to a next address signal prior to completion of a pending operation, said microcomputer system comprising:
a processor of a given bit width, PA0 a cache memory subsystem of said given bit width coupled to said processor by a local bus, PA0 a further bus connecting said local bus with other components having said given bit width and with at least one component of a reduced bit width, at least some of said components having said given bit width having an address in an address range associated with said cache subsystem and said at least one component of reduced bit width having an address outside an address range associated with said cache subsystem, wherein said microcomputer system further includes: PA0 a) address decoder means responsive to an asserted address on said local bus for generating a signal indicating whether said asserted address is or is not within said address range associated with said cache memory subsystem, and PA0 b) logic means responsive to said signal from said address decoder means for generating a next address signal to said microprocessor for pipelined operation unless said address decoder means indicates an asserted address outside a range associated with said cache subsystem.